RTLPreCheck reads raw SystemVerilog and generates formally proven properties automatically. No specifications. No manual assertions. No naming conventions. Just structure.
Traditional formal verification asks: given this spec, does the design comply? RTLPreCheck asks the opposite: given this design, what must be true? The structure reveals buffers, arbiters, pipelines, and exactly which formal properties each one must satisfy.
Reads raw RTL. Classifies every register cluster by behavioral role using AST topology, graph structure, and IR metadata alone.
Selects formal property templates for each classification. Register stability, deadlock freedom, drain liveness, mutual exclusion — all generated from structure.
Every property is proven via k-induction. Sound abstract models are built automatically for large modules. Anti-vacuity covers verify every proof is exercised.
Cross-module assume-guarantee contracts are extracted from proven probes and discharged automatically via geometry-based port matching.
Convolution DMA from NVIDIA’s Deep Learning Accelerator. Orchestrates all data movement between external memory and the compute engine.
March 30, 2026
63 modules analyzed across the full CDMA hierarchy — 5,883 registers, weight/feature/pixel data channels, shared buffer management, DMA mux, and multi-phase sequencing. Cold start, reproducible every run. 940 port connections validated across 3 hierarchy levels (100% netlist completeness).
The largest modules (2,500 to 6,200 registers) cannot be proven by bounded model checking. RTLPreCheck automatically constructs small abstract models that capture essential progress behavior, then validates via a soundness check against full concrete RTL. Both projects complete in seconds on modules where flat BMC would never converge. The abstraction, the soundness linkage, and the proof are all generated from structure. No manual abstractions, no helper logic, no cut points.
236 unique contract edges discharged across 63 modules. 940 port connections validated (100% netlist completeness). 193 external inputs cataloged as integration boundary candidates. Guarantees matched to assumptions via structural port matching over RTL wiring topology. Validated against Slang elaborated IR. Zero manual pairs.
If you’re working on a design that needs formal verification coverage, or if you’d like to see RTLPreCheck run on your RTL, reach out.
taylor@rtlprecheck.com