RTLPreCheck reads raw SystemVerilog and generates formally proven properties automatically. No specifications. No manual assertions. No naming conventions. Just structure.
Traditional formal verification asks: given this spec, does the design comply? RTLPreCheck asks the opposite: given this design, what must be true? The structure reveals buffers, arbiters, pipelines, and exactly which formal properties each one must satisfy.
Reads raw RTL. Classifies every register cluster by behavioral role using AST topology, graph structure, and IR metadata alone.
Selects formal property templates for each classification. Register stability, deadlock freedom, drain liveness, mutual exclusion — all generated from structure.
Every property is proven via k-induction. Sound abstract models are built automatically for large modules. Anti-vacuity covers verify every proof is exercised.
Cross-module assume-guarantee contracts are extracted from proven probes and discharged automatically via geometry-based port matching.
SmallBoomV3 from Chipyard
March 17, 2026
268 modules received automated formal analysis. Every proof ran on an open-source formal solver. The generated properties are standard SVA, portable to any commercial formal tool.
We injected a 3-line microarchitectural bug into BOOM's reorder buffer. When an exception and a branch mispredict arrive on the exact same cycle, a latch permanently blocks the commit pointer. The processor hangs. Simulation never triggers it.
Caught in 17 seconds with a concrete counterexample trace. The formal solver explores every reachable state — no random stimulus, no directed tests needed. This class of bug sits at the intersection of two independent recovery paths in the microarchitecture and is vanishingly rare in simulation across billions of cycles.
9,084 contract edges automatically discharged across 266 modules. Guarantees extracted from proven probes, matched to downstream assumptions via geometry-based port matching over RTL wiring topology. Transitive propagation through combinational paths. Zero manual pairs.
If you're working on a design that needs formal verification coverage, or if you'd like to see RTLPreCheck run on your RTL, reach out.
taylor@rtlprecheck.com